Title :
A 2.7 V only 8 Mb/spl times/16 NOR flash memory
Author :
Chen, J.C. ; Kuo, T.H. ; Cleveland, L.E. ; Chung, C.K. ; Leong, N. ; Kim, Y.K. ; Akaogi, T. ; Kasa, Y.
Author_Institution :
Adv. Micro Devices Inc., Sunnyvale, CA, USA
Abstract :
This paper describes a 80 ns, 2.7 V to 3.6 V single voltage supply 8 Mb/spl times/16 flash memory. It uses a high speed Vcc detector to control the wordline boost level and an intelligent programming algorithm to optimize the program time. Erase is achieved by a new low Vcc negative charge pump. The device is fabricated using a 0.5 /spl mu/m design rule, double layer metal, dual layer polysilicon, and triple well CMOS. The single transistor cell size is 1.7/spl times/1.7 /spl mu/m/sup 2/. The memory cell uses a conventional drain side channel hot electron for programming and negative gate Fowler-Nordheim tunneling on the source side for erase.
Keywords :
CMOS memory circuits; EPROM; NOR circuits; PLD programming; VLSI; hot carriers; tunnelling; 0.5 micron; 2.7 to 3.6 V; 8 Mbit; 80 ns; NOR flash memory; double layer metal; drain side channel hot electron programming; dual layer polysilicon; high speed Vcc detector; intelligent programming algorithm; negative charge pump; negative gate Fowler-Nordheim tunneling; single voltage supply; triple well CMOS process; wordline boost level control; Charge pumps; Detectors; Electrons; Flash memory; Tunneling; Voltage;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507759
