Title :
Hybrid phase locked loop system for PRML disk drive read channels
Author :
Kovacs, J. ; McCall, K.
Author_Institution :
Analog Devices Inc., Wilmington, MA, USA
Abstract :
This paper describes a mixed signal Phase Locked Loop sub-system in a Partial Response Maximum Likelihood (PRML) disk drive read channel IC fabricated on a single poly, dual metal 0.6 u, 5 V foundry CMOS process. The PLL provides programmable damping factor and gain control over a 25-200 MHz frequency range. A non-linear ADC improves its robustness when processing asymmetrical input signals. Acquisition time is reduced by instantaneously adjusting the start-up phase of its clock output.
Keywords :
CMOS integrated circuits; maximum likelihood detection; mixed analogue-digital integrated circuits; partial response channels; phase locked loops; 0.6 micron; 25 to 200 MHz; 5 V; PRML disk drive read channel IC; asymmetrical signal processing; gain control; mixed signal phase locked loop; nonlinear ADC; programmable damping factor; single poly dual metal foundry CMOS process; CMOS integrated circuits; CMOS process; Damping; Disk drives; Foundries; Frequency; Gain control; Phase locked loops; Robustness; Signal processing;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507761
