Design of a DVB-S receiver in FPGA

The paper deals with the design of an all-digital receiver for the DVB-S standard in FPGA. We describe the implementation issues of the next stages: digital acquisition at intermediate frequency, downconversion to baseband, synchronization in time, and synchronization in frequency and phase. The high data rates needed by this all-digital architecture can only be achieved by a latest generation FPGA and with a careful design of each subsystem. So, for each stage we propose the most efficient design for Xilinx FPGAs in terms of area and throughput. Finally, we present the implementation results of a complete DVB-S digital receiver on a Virtex-II Pro FPGA.