Skew minimization techniques for 256M-bit synchronous DRAM and beyond

A major issue in designing a high speed synchronous DRAM (SDRAM) is how to minimize skews, most of which are generated due lo unequal read/write data paths, different enable/disable times between column select lines (CSLs), unequal distribution of clock and unequal cell conditions. In this paper, we will present various circuit techniques for minimization of the skews to achieve the irtaxiiiium intemal clock frequency of a 256M-hit SDRAM.