• DocumentCode
    2126643
  • Title

    Noise suppression scheme for giga-scale DRAM with hundreds of I/Os

  • Author

    Takashima, D. ; Oowaki, Y. ; Watanabe, S. ; Ohuchi, K. ; Matsunaga, J.

  • Author_Institution
    ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
  • fYear
    1996
  • fDate
    13-15 June 1996
  • Firstpage
    196
  • Lastpage
    197
  • Abstract
    A new Constant Current Voltage-Down Converter and a new Partially Inverted data BUS Architecture are proposed. The proposed VDC reduces Vdd1/Vss1 noise to less than 20%, and the proposed BUS architecture reduces Vdd1/Vss1 noise to about 1/n using only n-1 bit flag signals.
  • Keywords
    DRAM chips; VLSI; convertors; integrated circuit noise; memory architecture; 1/n noise; VDC; constant current voltage-down converter; giga-scale DRAM; n-1 bit flag signals; noise suppression scheme; partially inverted data BUS architecture; Noise reduction; Random access memory; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
  • Conference_Location
    Honolulu, HI, USA
  • Print_ISBN
    0-7803-3339-X
  • Type

    conf

  • DOI
    10.1109/VLSIC.1996.507769
  • Filename
    507769
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2126643