Title :
Noise suppression scheme for giga-scale DRAM with hundreds of I/Os
Author :
Takashima, D. ; Oowaki, Y. ; Watanabe, S. ; Ohuchi, K. ; Matsunaga, J.
Author_Institution :
ULSI Res. Center, Toshiba Corp., Kawasaki, Japan
Abstract :
A new Constant Current Voltage-Down Converter and a new Partially Inverted data BUS Architecture are proposed. The proposed VDC reduces Vdd1/Vss1 noise to less than 20%, and the proposed BUS architecture reduces Vdd1/Vss1 noise to about 1/n using only n-1 bit flag signals.
Keywords :
DRAM chips; VLSI; convertors; integrated circuit noise; memory architecture; 1/n noise; VDC; constant current voltage-down converter; giga-scale DRAM; n-1 bit flag signals; noise suppression scheme; partially inverted data BUS architecture; Noise reduction; Random access memory; Voltage;
Conference_Titel :
VLSI Circuits, 1996. Digest of Technical Papers., 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3339-X
DOI :
10.1109/VLSIC.1996.507769
