ROS: an extremely high density mask ROM technology based on vertical transistor cells

Author

Bertagnolli, E. ; Hofmann, F. ; Willer, J. ; Mary, Rose ; Lau, F. ; von Basse, P.W. ; Bollu, M. ; Thewes, R. ; Kollmer, U. ; Zimmermann, U. ; Hain, M. ; Krautschneider, W.H. ; Rusch, A. ; Hasler, B. ; Kohlhase, A. ; Klose, H.

Author_Institution

Corp. Res. & Dev., Siemens AG, Munich, Germany

fYear

1996

fDate

11-13 June 1996

Firstpage

58

Lastpage

59

Abstract

A novel mask-ROM technology enabling a twofold packing density compared to conventional, planar ROM layout relying on the same design rules is presented. The key of the new technology is a cell concept based on a vertical MOS transistor in a trench, and a doubling of the bitline pitch by use of the trench bottom as additional bitline. The features of the ROS-technology are demonstrated by means of a 1 Mbit demonstrator memory. Since vertical transistors are manufacturable far below channel lengths of 100 nm, the technology is very promising for mass storage and thus for the replacement of conventional mass storage devices by semiconductor-memories.

Keywords

CMOS memory circuits; integrated circuit layout; integrated circuit technology; read-only storage; 1 Mbit; 100 nm; ROM layout; ROS-technology; bitline pitch doubling; high density mask ROM technology; semiconductor memories; trench; vertical MOS transistor; vertical transistor cells; MOSFETs; Read only memory; Semiconductor device manufacture;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507793

Filename

507793