DocumentCode :
2127388
Title :
Design of low error fixed-width squarer
Author :
Cho, Kyung-Ju ; Kim, Won-Kwan ; Kim, Byeong-Kuk ; Chung, Jin-Gyun
Author_Institution :
Dept. of Electron. & Inf. Eng., Chonbuk Nat. Univ., Chonju, South Korea
fYear :
2003
fDate :
27-29 Aug. 2003
Firstpage :
213
Lastpage :
218
Abstract :
The paper presents a design method for a fixed-width squarer that receives a W-bit input and produces a W-bit squared product. To compensate efficiently for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulation, it is shown that the performance of the proposed method is pretty close to that of the rounding operation and much better than that of the truncation operation.
Keywords :
digital arithmetic; error compensation; logic design; quantisation (signal); signal processing; Booth encoder outputs; digital signal processing applications; error compensation bias; fixed-width squarer; multiplier coefficients; quantization error; rounding operation; truncated bits; Design methodology; Digital signal processing; Encoding; Equalizers; Error compensation; Error correction; Frequency domain analysis; Image coding; Pattern recognition; Vector quantization;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signal Processing Systems, 2003. SIPS 2003. IEEE Workshop on
ISSN :
1520-6130
Print_ISBN :
0-7803-7795-8
Type :
conf
DOI :
10.1109/SIPS.2003.1235671
Filename :
1235671
Link To Document :
بازگشت