Optimal low power interconnect networks

Author

Davis, J.A. ; De, V. ; Meindl, J.

Author_Institution

Georgia Inst. of Technol., Atlanta, GA, USA

fYear

1996

fDate

11-13 June 1996

Firstpage

78

Lastpage

79

Abstract

Because interconnect capacitance represents the dominant load capacitance in CMOS VLSI systems, dynamic power dissipation is largely determined by multilevel wiring requirements. Using a newly derived stochastic interconnect distribution, a model for total on-chip power dissipation is developed. With this new model, the optimal interconnect dimensions for a multilevel network can be determined that minimize chip size and power drain.

Keywords

CMOS integrated circuits; VLSI; capacitance; circuit optimisation; integrated circuit design; integrated circuit interconnections; wiring; CMOS VLSI systems; chip size; dynamic power dissipation; interconnect capacitance; interconnect dimensions; load capacitance; low power interconnect networks; multilevel wiring requirements; on-chip power dissipation; power drain; stochastic interconnect distribution; Capacitance; Power dissipation; Power system interconnection; Power system modeling; Semiconductor device modeling; Stochastic processes; Very large scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507800

Filename

507800