Design and performance of SOI pass transistors for 1 Gbit DRAMs

Both partially and fully depleted NMOS pass transistors were designed and fabricated on SIMOX substrates. Using a p+ gate design, V/sub th/=1 V and I/sub off/<1 fA//spl mu/m was achieved on ultra thin film SOI pass transistors. With less than 1 fA//spl mu/m off-state leakage, the SOI pass transistor provides excellent DRAM cell retention time and low stand-by power. The pass transistor´s junction voltage decay after precharge is much slower on the thin film SOI than on thicker film SOI. In addition, the SOI pass transistors were found to have higher DRAM charging efficiency than the bulk pass transistor due to the elimination of the body effect. The higher charging efficiency of SOI pass transistors allows a reduction in the word line voltage during the charging state, avoiding the need for the usual boosting of the DRAM word line voltage, thereby increasing the gate oxide integrity and decreasing the active power.