High performance CMOS for GHz communication IC

Author

Tanabe, A. ; Togo, M. ; Soda, M. ; Tezuka, H. ; Suzaki, T. ; Furakawa, A. ; Emura, K.

Author_Institution

Microelectron. Res. Labs., NEC Corp., Kanagawa, Japan

fYear

1996

fDate

11-13 June 1996

Firstpage

134

Lastpage

135

Abstract

A 0.35 /spl mu/m design rule except for gate length was applied to CMOS ICs for giga hertz, low-power operation. To obtain such high speed switching, the gate was reduced to 0.15 /spl mu/m and parasitic capacitance was greatly reduced by a localized channel implant. Using this design technique, a 1:8 DEMUX for optical communication was developed, and has achieved high speed, low-power operation of 2.8 GHz/220 mW (@V/sub DD/=2 V) and 2.6 GHz/37 mW (@V/sub DD/=1 V). This technique was shown to be most effective in fields that require speeds greater than about 1 GHz but do not necessarily require large scale integration.

Keywords

CMOS digital integrated circuits; demultiplexing equipment; integrated circuit design; optical communication equipment; 0.15 micron; 0.35 micron; 1 to 2 V; 2.6 GHz; 2.8 GHz; 220 mW; 37 mW; CMOS; communication IC; demultiplexer; design rule; high speed switching; localized channel implant; low-power operation; optical communication; parasitic capacitance; CMOS integrated circuits; Communication switching; Implants; Large scale integration; Optical design; Optical fiber communication; Parasitic capacitance;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-3342-X

Type

conf

DOI

10.1109/VLSIT.1996.507822

Filename

507822