DocumentCode
2128683
Title
Gate oxide integrity (GOI) of MOS transistors with W/TiN stacked gate
Author
Lee, D.H. ; Yeom, K.H. ; Cho, M.H. ; Kang, N.S. ; Shim, T.E.
Author_Institution
Semicond. Res. & Dev. Center, Samsung Electron. Co. Ltd., Kyungki-Do, South Korea
fYear
1996
fDate
11-13 June 1996
Firstpage
208
Lastpage
209
Abstract
With W/TiN stack gate deposited at high temperature, excellent time-dependent dielectric breakdown (TDDB) characteristics of the gate oxide were obtained in MOS capacitors. In the case of negative gate bias where thin oxide reliability becomes critical, the TiN gate provides a much longer time to breakdown than that of n/sup +/-poly gate due to a larger barrier height and less F-N tunneling current. In spite of skipping the conventional reoxidation process, a breakdown field larger than 10 MV/cm could be obtained in MOS transistors by undercutting TiN with boiling H/sub 2/SO/sub 4/. With a double spacer and undercutting scheme, the short channel effect of NMOS and PMOS transistors could be suppressed up to L/sub gate//spl sim/0.3 /spl mu/m.
Keywords
CMOS integrated circuits; MOSFET; dielectric thin films; electric breakdown; integrated circuit metallisation; integrated circuit reliability; sputtered coatings; titanium compounds; tungsten; 0.3 micron; H/sub 2/SO/sub 4/; MOS transistors; NMOS transistors; PMOS transistors; TDDB characteristics; W-TiN-SiO/sub 2/-Si; W/TiN stacked gate; barrier height; breakdown field; double spacer; gate oxide integrity; high temperature deposition; negative gate bias; short channel effect suppression; thin oxide reliability; time-dependent dielectric breakdown; undercutting scheme; Dielectric breakdown; Electric breakdown; MOS capacitors; MOS devices; MOSFETs; Temperature; Tin; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-3342-X
Type
conf
DOI
10.1109/VLSIT.1996.507852
Filename
507852
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