Title :
A novel booster plate technology in high density NAND flash memories for voltage scaling-down and zero program disturbance
Author :
Choi, J.D. ; Kim, D.J. ; Tang, D.S. ; Kim, J. ; Kim, H.S. ; Shin, W.C. ; Ahn, S.T. ; Kwon, O.H.
Author_Institution :
Memory Div., Samsung Electron. Co. Ltd., Kyunkgki-Do, South Korea
Abstract :
The booster plate in NAND flash memory cells gives numerous advantages: the reduction of program, erase and pass voltages, zero program disturbance and increased cell current. At the same time, it is simple to integrate the technology to the conventional fabrication processes. It is expected that the booster plate technology will become one of the key technologies for achieving high density memories such as 256 Mbit and 1 Gbit NAND flash.
Keywords :
EPROM; NAND circuits; integrated circuit technology; integrated memory circuits; booster plate technology; cell current; fabrication; high density NAND flash memory; program disturbance; voltage scaling-down; Fabrication; Voltage;
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
DOI :
10.1109/VLSIT.1996.507863
