Title :
Read disturb degradation mechanism for source erase flash memories
Author :
Shuto, S. ; Yamada, S. ; Aritome, S. ; Watanabe, T. ; Hashimito, K.
Author_Institution :
Semicond. Device Eng. Lab., Toshiba Corp., Kawasaki, Japan
Abstract :
The read disturb degradation caused by source erase is studied. The anomalous Vth shift of about 1.0 V due to electron trapping is observed during read disturb. Vth shift due to electron trapping is more serious for high speed erase device. However, this Vth shift can be suppressed by using lower source voltage for erase.
Keywords :
EPROM; electron traps; integrated memory circuits; electron trapping; flash memory; high speed device; read disturb degradation; source erase; source voltage; threshold voltage; Degradation; Electron traps; Flash memory; Voltage;
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
DOI :
10.1109/VLSIT.1996.507865
