Title :
Process integration for the high speed NAND flash memory cell
Author :
Kim, D.J. ; Choi, J.D. ; Kim, J. ; Oh, H.K. ; Ahn, S.T. ; Kwon, O.H.
Author_Institution :
Memory Div., Samsung Electron. Co. Ltd., Kyungki-Do, South Korea
Abstract :
The high speed NAND flash memory cell with a read access time of 80 ns has been demonstrated. In the process integration of the high speed cell, complementary polycide bit lines with the ground selection scheme, self-aligned field through implantation, and metal source line have been introduced. The reliable high speed NAND cell operation has been achieved by enhanced sensing voltage swing, increased cell current and reduced bit line loading.
Keywords :
EPROM; NAND circuits; integrated circuit technology; integrated memory circuits; 80 ns; bit line loading; cell current; complementary polycide bit line; ground selection; high speed NAND flash memory cell; implantation; metal source line; process integration; self-aligned field; sensing voltage swing; Voltage;
Conference_Titel :
VLSI Technology, 1996. Digest of Technical Papers. 1996 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-3342-X
DOI :
10.1109/VLSIT.1996.507868
