Design issues for prototype implementation of a pipelined superscalar processor in programmable logic

This paper outlines design issues for a prototype implementation of a dual-issue superscalar processor architecture in programmable logic for the purpose of supporting research in application-specific system-on-chip design. The issues that are considered include fetching multiple instructions, forwarding for data hazard resolution, mapping the requirement for a multiported register file onto the constraints of embedded memory blocks in a programmable logic chip, and mapping the requirement for a larger cache block size onto a target environment with narrow external interfaces.