Title :
A low power 12-bit 10MS/s algorithmic ADC
Author :
Hai, N. ; Nairn, D.G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Waterloo, Waterloo, ON, Canada
Abstract :
A low power 12-bit 10MS/s algorithmic analog-to-digital converter (ADC) utilizing capacitor sharing and capacitor scaling techniques is presented. The techniques greatly reduce the power consumption of a typical algorithmic ADC. Power estimates are derived for the proposed technique, and other low power techniques. Circuit implementation details are presented along with simulated results. The ADC is expected to achieve a signal-to-noise-and-distortion ratio (SNDR) of 66dB while consuming 1mW from a 1.5V supply.
Keywords :
analogue-digital conversion; capacitors; low-power electronics; algorithmic analog-to-digital converter; capacitor scaling techniques; capacitor sharing techniques; circuit implementation; low power algorithmic ADC; low power techniques; power 1 mW; power consumption; power estimates; signal-to-noise-and-distortion ratio; voltage 1.5 V; word length 12 bit; Accuracy; Capacitance; Capacitors; Copper; Noise; Operational amplifiers; Power demand;
Conference_Titel :
Electrical and Computer Engineering (CCECE), 2010 23rd Canadian Conference on
Conference_Location :
Calgary, AB
Print_ISBN :
978-1-4244-5376-4
Electronic_ISBN :
0840-7789
DOI :
10.1109/CCECE.2010.5575206
