Title :
80 ps 30000 gates ECL gate array E-30000VH
Author :
Inoue, Takeyuki ; Mitono, Yoshiharu ; Takase, Masasi ; Nagaya, Kiyoe ; Minami, Kouta ; Miyazawa, Kipshi
Author_Institution :
Fujitsu Ltd., Kawasaki, Japan
Abstract :
The E-30000VH ECL (emitter-coupled-logic) gate array, which has a gate speed (with no load) of 80 ps and 30000 equivalent gates, is discussed. The E-30000VH features a three-level series gate circuit, a preimplemented clock distribution net of 150-ps skew, and 300 signal I/Os. The chip structure, internal gate circuit, and package are described. The results of gate speed measurements, using a ring oscillator, are reported
Keywords :
VLSI; bipolar integrated circuits; cellular arrays; emitter-coupled logic; logic arrays; packaging; 80 ps; E-30000VH; ECL gate array; VLSI; emitter-coupled-logic; gate speed measurements; internal gate circuit; package; preimplemented clock distribution net; ring oscillator; three-level series gate circuit; Adders; Capacitance; Clocks; Computer graphics; Large scale integration; Propagation delay; Resistors; System testing; Transistors; Very large scale integration;
Conference_Titel :
Bipolar Circuits and Technology Meeting, 1989., Proceedings of the 1989
Conference_Location :
Minneapolis, MN
DOI :
10.1109/BIPOL.1989.69451
