Thermal sensor variation reduction in deep sub 100nm process technologies

As technology scales, the impact of process variation to device and circuit performance has increased significantly. The presented statistical design approach illustrates the importance of pre-silicon circuit performance characterization under random variation stress. The measured data shows that by applying sound analog layout rules, actual variation can be reduced by 30% and that compensation techniques like chopping for amplifier offset cancellation and current source mismatch reduction are effective in lowering variation further by up to 55%. The choice between the static and dynamic application of these techniques is also discussed.