Title :
A highly-flexible FIR processor with scaleable dynamic data ranges
Author :
Liu, Wei-Lung ; Chen, Oscal T C ; Hsieh, Hsun-Chang ; Wang, Jeng-Yih
Author_Institution :
Dept. of Electr. Eng., Nat. Chung Cheng Univ., Taiwan, China
fDate :
31 May-3 Jun 1998
Abstract :
A highly-flexible finite impulse response (FIR) architecture with scaleable dynamic ranges of input data and filter coefficients is proposed based on the radix-4 Booth algorithm. In order to achieve scaleability, the configurable-connection function between input data latches and filter taps has been explored. The precision of filter coefficients is adjustable by using a path-control function. Especially, the proposed architecture only employs data-path controls to realize the scaleable issue without changing word lengths and components of input latches and filter taps. Based on our architecture, a typical FIR processor with 64-tap 8-bit and 32-tap 16-bit operations was implemented by using the COMPASS 5V cell library in the TSMC 0.6 μm CMOS technology. Its die size is around 8.0×8.0 mm2 with a power consumption of 2.9 W at a system clock of 100 MHz
Keywords :
CMOS digital integrated circuits; FIR filters; circuit stability; digital filters; integrated circuit design; 0.6 micron; 100 MHz; 16 bit; 2.9 W; 8 bit; CMOS technology; COMPASS 5V cell library; TSMC; configurable-connection function; die size; filter coefficients; filter taps; highly-flexible FIR processor; input data latches; input latches; path-control function; power consumption; radix-4 Booth algorithm; scaleable dynamic data ranges; system clock; CMOS process; CMOS technology; Computer architecture; Costs; Dynamic range; Energy consumption; Finite impulse response filter; Laboratories; Libraries; Partitioning algorithms;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.694518
