Fast FPGA-based area and latency estimation for a novel hardware/software partitioning scheme

In this paper a fast and accurate area and latency estimation tool for FPGA-based designs is presented. The tool is developed in the context of a HW/SW partitioning tool. Rather than modeling the hardware implementation as a single alternative, our approach for HW/SW partitioning models the hardware as two extreme alternatives that bound latency range for different hardware implementations. The presented estimation tool estimates the area and latency for these two hardware alternatives. The computational cost of the presented estimation tool depends linearly on the design complexity, and hence, it is very useful for fast design space exploration. Testing this estimation tool on several designs showed that this tool is also accurate. Area estimations are within plusmn7.5% of the actual number of logic elements consumed with an average error of 3.2% for Cyclone FPGAs and 3.5% for Stratix FPGAs.