An effective cache overlapping storage structure for SMT processors

Simultaneous multithreaded (SMT) processors improve the instruction throughput by allowing fetching and running instructions from several threads simultaneously at a single cycle. With the number of running threads increasing, the performance of single thread degrades continually. One main reason of that is the competition of the limited cache resources among the threads and then causing the number of cache misses of the single thread increasing dramatically. In this paper, we propose an effective cache overlapping storage structure for SMT processors. The key idea is using several bits to encode the value of a data. If the value is a frequent value, it can be read or written through the encoding scheme and a table of frequent value. All the frequent values are encoded in a determined way. Then all the bytes that store frequent values in a cache line can be used to store other values at the same positions of a different line that maps to the same physical hardware. We find that this overlapping structure is useful for SMT processors to alleviate the cache competing problem of the threads and increasing the cache hit rates of them. Comparing with the other schemes, our scheme needs less hardware or organizes the cache in a different way, and can read and write without adding much latency. The implementation of our structure is simple. Execution-driven simulation results show that with a little hardware adding to the original cache our structure obtains a performance near to that obtained from a double sized one in an SMT processor.