Digital beamforming developments for the joint NASA/Air Force Space Based Radar

The Space Based Radar (SBR) program includes a joint technology demonstration between NASA and the Air Force to design a low-earth orbiting, 2×50 m L-band (1.26 GHz) radar system for Earth science and intelligence-related observations. A key subsystem aboard SBR is the electronically-steerable digital beamformer (DBF) network that interfaces between 32 smaller subantenna panels in the array and the on-board processing electronics for Synthetic Aperture Radar (SAR) and Moving Target Indication (MTI). In this paper, we describe the development of a field-programmable gate array (FPGA) based DBF processor for handling the computationally intensive inner-product operations for wideband, coherent beamforming across the 50 m length of the array. The core functions of the DBF-the CORDIC (Coordinate Rotation Digital Computer) phase shifters and combiners-have been designed in the Verilog HDL (hardware description language) and implemented onto a high-density Xilinv Virtex II FPGA. This design achieves real-time processing at an input data rate of 25.6 Gbit/s. Tests with an antenna array simulator demonstrate that the beamformer performance metrics (0.07° rms phase precision per channel, -35.2 dB peak sidelobe level) will meet the system-level requirements for SAR and MTI operating modes.