DocumentCode
2133657
Title
Benefits of processor clustering in designing large parallel systems: when and how?
Author
Basak, Debashis ; Panda, Dhabaleswar K. ; Banikazemi, M.
Author_Institution
Dept. of Electr. Eng., Ohio State Univ., Columbus, OH, USA
fYear
1996
fDate
15-19 Apr 1996
Firstpage
286
Lastpage
290
Abstract
Advances in multiprocessor interconnect technology are leading to high performance network. However, software overheads associated with message passing are limiting the processors to get maximum performance from these networks, leading to under-utilization of network resources. Though processor clusters are being used in some systems in an ad hoc manner to alleviate this problem, there is no formal analysis in the literature to show when and how processor clusters benefit in designing high performance and scalable systems. In this paper we analyze and solve this problem by considering processor-clustering, messaging overheads, and network performance in an integrated manner. Our analysis establishes the following three design guidelines. Compared to a base system, under high messaging overheads, processor clustering can be used to build a) an equal-sized system with a smaller network or b) a larger system with an equal-sized network. Under low messaging overheads, a combination of processor clustering and wider channels can be used to build a range of larger-sized systems. All these guidelines lead to designing cost-effective and scalable parallel systems while delivering high performance
Keywords
message passing; multiprocessor interconnection networks; performance evaluation; high performance network; large parallel systems; messaging overheads; multiprocessor interconnect technology; network performance; processor clustering; processor-clustering; scalable systems; software overheads; Bandwidth; Computer networks; Guidelines; High performance computing; Information science; Message passing; Multiprocessor interconnection networks; Packaging; Performance analysis; Process design; Routing; Software performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel Processing Symposium, 1996., Proceedings of IPPS '96, The 10th International
Conference_Location
Honolulu, HI
Print_ISBN
0-8186-7255-2
Type
conf
DOI
10.1109/IPPS.1996.508071
Filename
508071
Link To Document