Experimental and Numberical Method of Measuring Flip Chip Die Bump Temperature for Electroncis Packing

Recent trends in the semiconductor industry are driving a continuous increase in current draw, but require a lighter, more compact and thinner packaging technology. As the electrical current through the controlled-collapse-chip-connection flip chip die bump increases, it results in increased bump and trace temperatures due to the Joule heating. Increasing electrical current and temperature have compounding effects on the electro-migration failure of the flip chip die bumps. This has necessitated the development of a measurement method to quantify the flip chip die bump temperature. This paper discusses the methodology of numerically predicting the flip chip die bump temperature. A numerical scheme is introduced which utilizes a multi-scale technique consisting of both a global model (in millimeters) and a local model (in microns). The local model, which is a subset of the global model, consists of a section of the die metal layers, flip chip bumps, and the multiple package layers. It utilizes temperature boundary conditions generated from the global model to ensure self-consistency in the approach. The local model is then used to determine the hottest temperature in the studied bumps. The current carrying capability of the bump can then be determined by the temperature value predicted