DocumentCode :
2134256
Title :
System-Level Thermal Performance Optimization for Electronic Module Incorporating Dual-Channel Power Stage For Digital Amplifier
Author :
Chiriac, Victor Adrian ; Lee, Tien-Yu Tom
Author_Institution :
Adv. Packaging & Syst. Integration, Freescale Semicond. Inc., Tempe, AZ
fYear :
2006
fDate :
May 30 2006-June 2 2006
Firstpage :
380
Lastpage :
386
Abstract :
A detailed numerical study was conducted to model the thermal behavior of a microelectronics module in a custom environment. The system incorporates four 54-lead small outline integrated circuit (SOIC) packages with exposed pads. These packages were coupled to a heat sink at a free convection environment with an external ambient temperature of 25 degC. The system is optimized by choosing the appropriate heat sink for the efficient operation of the device under constant powering, also is used to quantify the thermal impact of each element on the overall thermal performance of the module. The thermal performance for a maximum powering scenario is evaluated, and the peak field-effect transistor (FET) power levels satisfying the thermal budget (150degC) are identified. Several cases were investigated, varying the power levels and the thermal properties of the interfacing pads while maintaining the ambient temperature at 25degC. The peak temperatures for the typical (1.25 W/package) and maximum powering (3.3 W/package) scenarios range from 68degC to 132.5degC, indicating that both designs satisfy the thermal requirements; the corresponding junction-to-ambient thermal resistances (Rja) vary from 8.1degC/W to 8.8degC/W. An additional study evaluates two cases with an improved thermal pad with a thermal conductivity of 20 W/mK, replacing the existing pads, which have a thermal conductivity of 1.1 W/mK. This results in a peak temperature drop by 40degC. The corresponding stack-up thermal resistances were calculated for each layer, and indicate that most of the junction-to-ambient thermal resistance came from the thermal pad and heat sink (HS)-to-ambient thermal resistances. These resistances could be further reduced by applying forced convection to cool the system (thus reducing the heat sink-to-ambient thermal resistance), or by replacing the thermal pads with an improved thermal interface material. The temperature of the heat sink base is fairly uniform, indicat- - ing a good lateral heat spreading provided by the heat sink. The thermal interaction between the components is minimal, and could be further reduced when adding a better thermal interface between the package and heat sink
Keywords :
field effect transistors; heat sinks; integrated circuit packaging; modules; power amplifiers; thermal conductivity; thermal management (packaging); 150 C; 68 to 132.5 C; SOIC packages; digital amplifier; dual-channel power stage; electronic module; field-effect transistor; heat sink; interfacing pads; junction-to-ambient thermal resistances; microelectronics module; small outline integrated circuit packages; system-level optimization; thermal budget; thermal conductivity; thermal interface material; thermal performance optimization; thermal properties; Electronic packaging thermal management; FETs; Heat sinks; Integrated circuit packaging; Optimization; Power amplifiers; Temperature; Thermal conductivity; Thermal force; Thermal resistance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Thermal and Thermomechanical Phenomena in Electronics Systems, 2006. ITHERM '06. The Tenth Intersociety Conference on
Conference_Location :
San Diego, CA
ISSN :
1087-9870
Print_ISBN :
0-7803-9524-7
Type :
conf
DOI :
10.1109/ITHERM.2006.1645368
Filename :
1645368
Link To Document :
بازگشت