A decimal-to-decimal antilogarithmic converter

Author

Chen, Dongdong ; Zhang, Yu ; Chen, Li ; Teng, Daniel ; Wahid, Khan ; Ko, Seok-Bum

Author_Institution

Dept. of Electr. & Comput. Eng., Saskatchewan Univ., Saskatoon, SK

fYear

2008

fDate

4-7 May 2008

Abstract

This paper presents a novel design and implementation of a 7-digit fixed-point decimal-to-decimal antilogarithmic converter. A linear approximation algorithm is proposed and simulated in MATLAB models. The maximum absolute error of the proposed decimal antilogarithmic converter is in the range of -0.000999 les E_absolute les 0.000857 and the maximum percent error is in the range of -0.000715 les E_percent les 0.000691. The proposed decimal-to-decimal antilogarithmic converter is modeled in VHDL and implemented using a Xilinx Virtex-II Pro P30 FPGA device. The converter is implemented using combinational logic only and it computes decimal antilogarithms results in a single clock cycle, running at 53.1 MHz.

Keywords

convertors; field programmable gate arrays; fixed point arithmetic; 7-digit fixed-point converter; MATLAB models; Xilinx Virtex-II Pro P30 FPGA device; combinational logic; decimal-to-decimal antilogarithmic converter; frequency 53.1 MHz; linear approximation algorithm; maximum absolute error; Approximation algorithms; Computational modeling; Digital arithmetic; Field programmable gate arrays; Floating-point arithmetic; Hardware; Linear approximation; MATLAB; Mathematical model; Signal processing algorithms; Decimal-to-decimal Antilogarithmic Converter; FPGA;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2008. CCECE 2008. Canadian Conference on

Conference_Location

Niagara Falls, ON

ISSN

0840-7789

Print_ISBN

978-1-4244-1642-4

Electronic_ISBN

0840-7789

Type

conf

DOI

10.1109/CCECE.2008.4564734

Filename

4564734