Title :
Wiring space estimation for ECL gate arrays
Author_Institution :
Nat. Semicond., Santa Clara, CA, USA
Abstract :
An empirical formula that predicts the wiring tracks to be supplied for emitter-coupled-logic (ECL) gate arrays is derived, and factors that influence wiring requirements are explored. The relationship between supplied tracks and the number of cells/gates is a power function. The concept of gate equivalence is introduced to provide a common basis for comparing the different arrays, and a method for calculating the gate equivalence is proposed
Keywords :
bipolar integrated circuits; cellular arrays; circuit layout; emitter-coupled logic; logic arrays; logic design; ECL gate arrays; emitter-coupled-logic; gate equivalence; logic IC layout design; wiring space estimation; wiring tracks; Degradation; Equations; Integrated circuit interconnections; Logic arrays; Logic functions; Logic gates; Resistors; Routing; Wires; Wiring;
Conference_Titel :
Bipolar Circuits and Technology Meeting, 1989., Proceedings of the 1989
Conference_Location :
Minneapolis, MN
DOI :
10.1109/BIPOL.1989.69454
