Thin film thermoelectric cooler thermal validation and product thermal performance estimation

The shrinking transistor feature sizes have resulted broadly in two different packaging thermal challenges; cooling the total thermal design power of the microprocessor, and thermal suppression of the hot spots which have progressively higher heat fluxes through silicon generations. Solid-state thin film thermoelectric coolers offer a possible solution strategy to the hot spot problems by mitigating the thermal non-uniformity of the silicon. However, considerable challenges are present in incorporating the thermoelectric coolers into a test device and thermal characterization of the prototypes. The present work captures the experimental and thermal modeling methodology that was used to characterize the thermal-electrical behavior of the prototypes. This characterization was followed up with a validation of the prototype over a range of uniform and hot spot heating. A temperature variation of less than 1degC in T_j between the experimental and modeling results were seen. In addition, less than 3% variation in electrical current supplied to the TFTEC module was seen between the experimental and modeling results. Based on the validated thermal model, a product use-condition modeling methodology was established in which the non-uniform heating of the product in use-condition was considered. This methodology was demonstrated using a product example and the hot spot temperature suppression was estimated to be 6degC, compared to the case when no thermoelectric cooler was used. Several interesting phenomena such as creation of new hot spots around the TFTEC module region were also observed