Use-condition thermal metrics for characterization of thin film TEC modules on electronic packages

Decrease in the transistor features have resulted in increased challenges of cooling the hotspots in addition to cooling the overall die. In addition, future packaging concepts of stacked die exacerbate the need for spot-cooling thermal solution. Thin film thermoelectric modules [TFTEC] are increasingly being investigated as a solution to hot-spot cooling. However, integration of the thermoelectric pellets into a TFTEC module, and subsequent assembly in an electronic package induces thermoelectric parasitic effects [eg. thermal-electrical contact resistance] that can hamper the performance of the TFTEC modules. In this work, a novel methodology is proposed for defining a "module ZT" based on the module stackup and the use-condition boundary conditions. The significance of this work is that the "module ZT" captures the relative importance of the assembly-related parasitic effects and boundary conditions during operation compared to the intrinsic thermoelectric properties of the TE material. These factors have not been considered in the more traditional definition of "intrinsic" material ZT. A generic methodology and expression is also derived and established for the estimation of the module ZT of the assembled TFTEC module, which incorporates impact of the TFTEC assembly process on the thermoelectric performance of the module in "use-condition". Thermoelectric modeling was performed to confirm the validity of the metric. For example, two intrinsically different thermoelectric materials with 40% difference in intrinsic ZT were derived to have comparable module ZT [2% variation]. The accompanying numerical analysis for these two cases predicted comparable temperature suppression with the use of TFTEC coolers with a variation of less than 0.1degC. The range of applicability and limitations of this metric is also discussed in this work