• DocumentCode
    2135713
  • Title

    Stabilizing Path Modification of Power-Aware On/Off Interconnection Networks

  • Author

    Montañana, Jose Miguel ; Koibuchi, Michihiro ; Matsutani, Hiroki ; Amano, Hideharu

  • Author_Institution
    Nat. Inst. of Inf., Tokyo, Japan
  • fYear
    2010
  • fDate
    15-17 July 2010
  • Firstpage
    218
  • Lastpage
    227
  • Abstract
    Power saving is required for interconnects of modern PC clusters as well as the performance improvement. To reduce the power consumption of switches with maintaining the performance, on/off link regulations that activate and deactivate the links based on the traffic load have been widely developed in interconnection networks. Depending on which operation is selected, link activation or deactivation, the available network resources are changed, thus requiring paths to be reconfigured. To maintain deadlock freedom of packet transfers, connectivity, and performance during the path changes, we propose to apply dynamic reconfiguration techniques that process packet transfer uninterruptedly to power-aware on/off interconnection networks. The dynamic network reconfiguration techniques stabilize the update of paths that are quite crucial to use power-aware on/off link techniques in interconnects of PC clusters. We investigate the performance and behavior of network reconfiguration technique as soon as the link activation or deactivation occurs. Evaluation results show that the simple dynamic reconfiguration techniques slightly reduce the peak packet latency and reconfiguration time of the change compared with existing static reconfiguration in on/off interconnection networks. A reconfiguration technique called Double Scheme reduces by up to 95% the peak packet latency caused by the on/off link operation.
  • Keywords
    power aware computing; power consumption; workstation clusters; PC cluster; dynamic reconfiguration technique; on-off link regulations; path modification; power saving; power-aware on-off interconnection networks; Clustering algorithms; Control systems; Multiprocessor interconnection; Process control; Routing; Strontium; System recovery;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Networking, Architecture and Storage (NAS), 2010 IEEE Fifth International Conference on
  • Conference_Location
    Macau
  • Print_ISBN
    978-1-4244-8133-0
  • Type

    conf

  • DOI
    10.1109/NAS.2010.13
  • Filename
    5575649