• DocumentCode
    2136309
  • Title

    Verification of multi-valued logic networks

  • Author

    Drechsler, Rolf

  • Author_Institution
    Inst. of Comput. Sci., Albert-Ludwigs-Univ., Freiburg, Germany
  • fYear
    1996
  • fDate
    29-31 May 1996
  • Firstpage
    10
  • Lastpage
    15
  • Abstract
    A method for verification of Multi-Valued Logic Networks (MVLNs) using Ordered Multi-Valued Decision Diagrams (OMDDs) is presented. For tree-like MVLNs an upper bound on the OMDD size can be proven. Thus, heuristics known for OBDDs can also be used for OMDDs. A large set of experiments is presented that underlines the efficiency of the approach
  • Keywords
    directed graphs; formal verification; logic testing; multivalued logic circuits; directed acyclic graph; functional equivalence; heuristics; multi-valued logic networks verification; ordered multi-valued decision diagrams; two-valued circuits; Boolean functions; Circuits; Computer science; Data structures; Design automation; Design methodology; Libraries; Logic design; Multivalued logic; Upper bound;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Multiple-Valued Logic, 1996. Proceedings., 26th International Symposium on
  • Conference_Location
    Santiago de Compostela
  • ISSN
    0195-623X
  • Print_ISBN
    0-8186-7392-3
  • Type

    conf

  • DOI
    10.1109/ISMVL.1996.508329
  • Filename
    508329
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2136309