• DocumentCode
    2136789
  • Title

    The fallacy of spec-based design

  • Author

    Bhatt, Rahul ; LaFollette, Dave ; Kapur, Arjun

  • Author_Institution
    Intel Corp., Santa Clara, CA, USA
  • fYear
    2003
  • fDate
    22-27 Sept. 2003
  • Firstpage
    156
  • Lastpage
    162
  • Abstract
    The architectural reference model, a critical tool in microprocessor validation, serves as a gold standard against which a microprocessor is compared. As all validation is performed using it, the reference model must be timely, extensible beyond the original specification, customizable for specific usage models, and, most importantly, functionally flawless. Ideally, we would like a specification-based design flow that transforms the published English language specifications into compilable code that is directly incorporated into the reference model without loss of information or accuracy. At Intel, we have developed and implemented such a flow to create the Itanium Processor Family´s (IPF) reference model, which is used to validate all IPF processors. In this paper, we describe the benefits and limitations of this process and discuss the practical implications of specification-based design.
  • Keywords
    formal specification; formal verification; microprocessor chips; parallel architectures; performance evaluation; English language specifications; IPF processor validation; Itanium/spl reg/ processor family; architecture reference model; formal specification; microprocessor validation; specification-based design flow; Computer architecture; Context modeling; Encoding; Formal specifications; Gold; Hardware; Manuals; Microprocessors; Natural languages; Software systems;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Software Engineering and Formal Methods, 2003.Proceedings. First International Conference on
  • Conference_Location
    Brisbane, Queensland, Australia
  • Print_ISBN
    0-7695-1949-0
  • Type

    conf

  • DOI
    10.1109/SEFM.2003.1236217
  • Filename
    1236217