Title :
Computational Modeling of the Reliability of Stacked Low Density Interconnects Devices
Author :
Hossain, Mohammad M. ; Lee, Yongje ; Akhter, Roksana ; Agonafer, Dereje ; Dishongh, Terry
Author_Institution :
Texas Univ., Arlington, TX
fDate :
May 30 2006-June 2 2006
Abstract :
As consumers demand more functions in their hand-held devices, the need for more memory in a limited space is increasing. Over the past few years, die stacking has emerged as a powerful method for satisfying challenging IC packaging requirements. Traditionally, chip stacking was carried out with dies of different sizes so the top die was always smaller than the bottom die to permit wire bonding of both. Today, it´s common to see the stacking of same-size dies or a larger die over a smaller one. Spacer or dummy die are also placed to accommodate two same-size dies. Different die orientations like staggered and rotational stacking can be done only if the dies are rectangular. Previous thermal analysis study on various die stacking architectures, which are commonly, employed in semiconductor flash products shows that thermal issues are not dominant for stacked die configuration (Kada and Smith, 2000). This leads to this current study to investigate the effect of thermo-mechanical stresses. As there are existence of multiple die and other material with different CTEs, thermo-mechanical loading and its effect on reliability needs to be studied for optimum die configuration. This study focuses on viscoplastic finite-element simulation to predict the solder joint fatigue life of different die stacking architectures for flash memory applications. Four different stacked package architectures were evaluated as follows: (1) pyramid stack, (2) rotated stack, and (3) stacking with spacers, (4) staggered die stacking; while interconnection architecture (solder joint) was held constant. Die stacking number for four different stacking configurations were varied from three, five and seven keeping the package height constant. A quarter symmetry and half symmetry model of stacked flash package are generated using ANSYS as a finite element solver. Models are simulated under accelerated temperature cycling conditions (-40degC to +125degC, 15min ramps/15min dwells). Fatigue life and pla- - stic strain accumulation results are presented in the paper. Results show that significant differences in plastic strain accumulation and fatigue life differences for different geometrical die configuration. Effects of different package reliability package reliability parameters like die size, die and die attach thickness are were varied and the effects of stresses due to that were discussed in this paper
Keywords :
fatigue; flash memories; integrated circuit interconnections; integrated circuit packaging; integrated circuit reliability; microassembling; soldering; solders; -40 to 125 C; 3D stack package; ANSYS; IC packaging; chip stacking; fatigue life; finite element modeling; finite element solver; flash memory; geometrical die configuration; hand-held devices; memory application; pyramid stack; rotated stack; spacer stacking; stacked die configuration; stacked low density interconnects devices; staggered die stacking; thermal analysis; thermo-mechanical stresse; viscoplastic finite-element simulation; Bonding; Capacitive sensors; Computational modeling; Fatigue; Finite element methods; Integrated circuit packaging; Soldering; Stacking; Thermomechanical processes; Wire;
Conference_Titel :
Thermal and Thermomechanical Phenomena in Electronics Systems, 2006. ITHERM '06. The Tenth Intersociety Conference on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-9524-7
DOI :
10.1109/ITHERM.2006.1645466