Thermo-mechanical simulation of stacked chip scale packages with moire interferometry vaildation

Author

Johnson, Zane E. ; Schneck, Nathan R. ; Thoreson, Andrew R. ; Stone, James J.

Author_Institution

Center for Nanoscale Sci. & Eng., North Dakota State Univ., Fargo, ND

fYear

2006

fDate

May 30 2006-June 2 2006

Firstpage

1120

Lastpage

1125

Abstract

Moire interferometry and finite element (FE) analysis are used to quantify the deformation of stacked chip scale packages under thermal and accelerated thermal cycling loads. Basic thermo-elastic material property measurements are made of the constituent materials and found to be in good agreement with published values. Viscoplastic FE-based solder joint fatigue simulations indicate good reliability for several common design configurations of stacked packages

Keywords

chip scale packaging; fatigue; finite element analysis; integrated circuit reliability; light interferometry; moire fringes; multichip modules; soldering; viscoplasticity; MCM; Moire interferometry; chip scale package; finite element analysis; multi chip module; stacked chip scale packages deformation; tensile test; thermal cycling loads; thermo-mechanical simulation; viscoplastic solder joint fatigue; Acceleration; Chip scale packaging; Fatigue; Finite element methods; Interferometry; Material properties; Semiconductor device measurement; Soldering; Thermal loading; Thermomechanical processes;

fLanguage

English

Publisher

ieee

Conference_Titel

Thermal and Thermomechanical Phenomena in Electronics Systems, 2006. ITHERM '06. The Tenth Intersociety Conference on

Conference_Location

San Diego, CA

ISSN

1087-9870

Print_ISBN

0-7803-9524-7

Type

conf

DOI

10.1109/ITHERM.2006.1645470

Filename

1645470