DocumentCode
2137672
Title
Theoretical model based thermal studies on stacked dies
Author
Saini, Manish
Author_Institution
Digital Enterprise Group, Intel Corp., Hillsboro, OR
fYear
2006
fDate
May 30 2006-June 2 2006
Lastpage
1219
Abstract
A generic thermal resistance based theoretical model is proposed for n ges 3 stacked dies. The model assumes same die to die thermal resistance between adjacent dies. It also includes external thermal resistances. This model is solved to establish the relation between thermal resistances and total heat flow from top and bottom of package. The hottest die location is related to the ratio of total heat going through top of the package, ´F´. This relation is found to be stair case like linear function. Lower and upper bounds to the temperature drop within the die stack are established. Two definitions of package thermal metrics are proposed. Both are shown to have a quadratic variation with the fraction of total heat going through top of the package (F). The results form a scientific basis for steady state thermal characterization of 3D stacked dies under complete range of external thermal boundary conditions
Keywords
functions; integrated circuit modelling; integrated circuit packaging; temperature distribution; thermal resistance; 3D stacked dies; heat flow; hottest die location; linear function; package thermal metrics; thermal characterization; thermal resistance; Boundary conditions; Resistance heating; Resistors; Semiconductor device packaging; Steady-state; Technology management; Temperature; Thermal management; Thermal resistance; Upper bound;
fLanguage
English
Publisher
ieee
Conference_Titel
Thermal and Thermomechanical Phenomena in Electronics Systems, 2006. ITHERM '06. The Tenth Intersociety Conference on
Conference_Location
San Diego, CA
ISSN
1087-9870
Print_ISBN
0-7803-9524-7
Type
conf
DOI
10.1109/ITHERM.2006.1645483
Filename
1645483
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