Extraction of parallel hardware during C to VHDL translation

Author

Chen, Jie ; Haggard, Roger L.

Author_Institution

Dept. of Electr. & Comput. Eng., Tennessee Technol. Univ., Cookeville, TN, USA

fYear

2002

fDate

2002

Firstpage

334

Lastpage

338

Abstract

Translating C/C++ language into VHDL is an important step in synthesizing hardware from C/C++. However, there is no explicit facility in the general C/C++ language to declare concurrent parallel execution which is a critical characteristic of hardware systems. This paper presents the outline of a set of transformation algorithms. These algorithms are helpful in the process of extracting parallel hardware during C to VHDL translation. An example of extracting parallel hardware from an array addition routine written in C is also presented in this paper.

Keywords

C language; hardware description languages; hardware-software codesign; parallel architectures; program interpreters; C language; C++ language; VHDL; concurrent parallel processing; parallel architecture; program translation; routine; transformation algorithms; Algorithm design and analysis; Circuit synthesis; Concurrent computing; Data mining; Distributed computing; Field programmable gate arrays; Hardware; Parallel architectures; Parallel processing; Partitioning algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

System Theory, 2002. Proceedings of the Thirty-Fourth Southeastern Symposium on

ISSN

0094-2898

Print_ISBN

0-7803-7339-1

Type

conf

DOI

10.1109/SSST.2002.1027062

Filename

1027062