Applying the small-world network to routing structure of FPGAs

The degree of integration and the operating frequency of programmable logic have improved dramatically with the development of new process technologies. However, for the deep sub-micron processes, the delay, reliability, cost, and power tend to be determined by interconnections. In conventional programmable logic, reducing the number of switches on a critical path is important because the wiring delay is considerably smaller than the switch delay. However, to achieve a decrease in the critical path delay it is also necessary to consider the wiring delay for the deep sub-micron processes. This paper proposes a novel routing structure using a small-world network structure for the interconnection of programmable logic. This paper demonstrates that the critical path delay can be reduced. Based on the results of an evaluation, the authors show that the critical path delay can be reduced by a maximum of 15% and the amount of routing resources can be reduced by a maximum of 23% when using the small-world network structure.