Dynamic Circuit Analysis and Testing for International Space Station Science Experiments

The International Space Station (ISS) Payload Engineering Integration (PEI) organization has developed the critical capabilities in dynamic circuit modeling and simulation to analyze electrical system anomalies during testing and operation. This presentation provides an example of the processes, tools and analytical techniques applied to the improvement of science experiments over-voltage clamp circuit design which is widely used by ISS science experiments. The voltage clamp circuit of Science Rack exhibits parasitic oscillations when a voltage spike couples to the field-effect transistor (FET) in the clamp circuit. The oscillation can cause partial or full conduction of the shunt FET in the circuit and may result in the destruction of the FET. In addition, the voltage clamp circuit is not designed to detect the high current through the FET, and this condition can result in damage to surrounding devices. The potential oscillation and the potential over-current, which could result in the destruction of the FET and surrounding devices, were analyzed by dynamic circuit simulation and tests. Test results show that the clamp circuit is highly susceptible to the false turn-on and parasitic oscillation when a voltage spike is coupled to the gate through the gate-to-drain capacitance or the diode capacitance. Circuit component analysis, based on FET parasitic inductance and capacitance, indicates that the frequency of parasitic oscillation falls in the range of 65 MHz to 80 MHz. The test results also show that a 100 ohms resistor in series with the FET gate eliminates parasitic oscillation while limiting the charging current at turn-on. Additionally, modeling results show that if the voltage is clamped, the FET current may exceed the operating region defined by the FET manufacturer, International Rectifier. This dynamic modeling provides essential design information for the set points of the current to flow through the FET. Engineering experience with power FET circuits has- - shown that they are prone to spurious activation if the circuit does not provide adequate damping. False turn-on of the FET circuit may cause sustained oscillations and damage the circuit. The test results and analytical models discussed in this paper reveals that parasitic oscillations can be effectively eliminated with a series resistor on the gate circuit of FET and this should be included as an important design consideration for the electrical power distribution circuits