DocumentCode :
2138413
Title :
Error modelling of dual fixed-point arithmetic and its application in field programmable logic
Author :
Ewe, Chun Te ; Cheung, Peter Y K ; Constantinides, George A.
Author_Institution :
Dept. of Electr. & Electron. Eng., Imperial Coll. London, UK
fYear :
2005
fDate :
24-26 Aug. 2005
Firstpage :
124
Lastpage :
129
Abstract :
Dual FiXed-point (DFX) is a new data representation which is an efficient compromise between fixed-point and floating-point representations. DFX has an implementation complexity similar to that of a fixed-point system with the improved dynamic range capability of a floating-point system. Automating the process of DFX scaling optimisation requires the knowledge of its truncation/rounding noise properties. This paper presents truncation and rounding error models for DFX arithmetic as traditional error models do not apply to DFX. The models were tested on a 159-tap FIR filter and the benefits of using DFX over floating-point are demonstrated with implementations on a Xilinx Virtex II Pro.
Keywords :
computational complexity; data structures; floating point arithmetic; roundoff errors; scaling circuits; 159-tap FIR filter; DFX arithmetic; DFX scaling optimisation; Xilinx Virtex II Pro; dual fixed-point; dual-fixed point arithmetic; fixed-point and floating-point representations; fixed-point system; floating-point system; implementation complexity; improved dynamic range; new data representation; rounding noise properties; truncation; Dynamic range; Field programmable gate arrays; Finite impulse response filter; Finite wordlength effects; Fixed-point arithmetic; Floating-point arithmetic; Programmable logic arrays; Programmable logic devices; Roundoff errors; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications, 2005. International Conference on
Print_ISBN :
0-7803-9362-7
Type :
conf
DOI :
10.1109/FPL.2005.1515710
Filename :
1515710
Link To Document :
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