Analysis and designing of the stable parallel packet switch

Author

Dong, Yuguo ; Li, Zupeng ; Liu, Xiaodong ; Guo, Yunfei

Author_Institution

Nat. Digital Switching Syst. Eng. & Technol. R&D Center, Zhengzhou, China

fYear

2003

fDate

27-29 Aug. 2003

Firstpage

296

Lastpage

300

Abstract

The parallel packet switch attracts a lot of attention from the communications equipment vendors since it can be practically applied into terabit switches and routers. In order to accelerate its recognition and deployment, we attempt to present the detailed analysis of stability for the parallel packet switch architecture. A model of the stable parallel packet switch (SPPS) is proposed. Then the constraints of traffic dispatch algorithms, the number of layers and internal speedup for the SPPS are theoretically analyzed. Based on these results an example of designing SPPS architecture with 1.28 T capacity is presented. Simulations were carried out to investigate the validity and practicality of the designed SPPS.

Keywords

packet switching; queueing theory; resource allocation; telecommunication traffic; buffer internal speedup; load-balancing; multiqueue system; network routers; network traffic dispatch algorithm constraints; packet buffer; stable parallel packet switch architecture; terabit switches; Aggregates; Algorithm design and analysis; Communication switching; Packet switching; Stability analysis; Switches; Switching systems; Systems engineering and theory; Telecommunication switching; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Parallel and Distributed Computing, Applications and Technologies, 2003. PDCAT'2003. Proceedings of the Fourth International Conference on

Print_ISBN

0-7803-7840-7

Type

conf

DOI

10.1109/PDCAT.2003.1236309

Filename

1236309