Title :
On the load balancing of a parallel switch with input queues
Author :
Dong, Yuguo ; Yi, Peng ; Guo, Yunfei ; Wu, Jiangxin
Author_Institution :
Nat. Digital Switching Syst. Eng. & Technol. R&D Center, Zhengzhou, China
Abstract :
The parallel switch is an emerging switch technology, by which we can build a high capacity switching system, such as a terabit switch, from many small switch fabrics. In a parallel switch with input queues, the high-speed packets will queue in the input buffer for scheduling, which can highly reduce the control complexity and the internal speedup. We refer to parallel switch with input queues as buffered parallel switch (BPS). Since the switch fabrics in a BPS are working parallel and independently, we address the open issue of switch fabrics´ load-balancing and propose a family of distributed scheduling algorithms. We also prove that such load-balancing algorithms can guarantee the delay time of the BPS. Simulation results show the validity and performance of our load-balancing algorithm. Practical considerations on implementing the scheduling algorithms are discussed.
Keywords :
processor scheduling; queueing theory; resource allocation; telecommunication traffic; BPS; buffer internal speedup; buffer scheduling; buffered parallel switch; control complexity; distributed scheduling algorithm; high-speed packets; input queues; load balancing algorithm; switch fabrics; terabit switch; Aggregates; Fabrics; Load management; Packet switching; Scheduling algorithm; Switches; Switching systems; Systems engineering and theory; Telecommunication switching; Traffic control;
Conference_Titel :
Parallel and Distributed Computing, Applications and Technologies, 2003. PDCAT'2003. Proceedings of the Fourth International Conference on
Print_ISBN :
0-7803-7840-7
DOI :
10.1109/PDCAT.2003.1236310