Defect tolerance in multiple-FPGA systems

SRAM-based FPGAs have an inherent capacity for defect tolerance. We propose a simple scheme that exploits this potential in multiple-FPGA systems. The symmetry of the system is exploited to yield a large number of possible mappings of bitstreams on FPGAs, which results in a high probability that at least one functional mapping exists. We show that the behavior of a system built using a large number of defective FPGAs approaches that of the ideal defect-free system. Various interconnection topologies such as the tree, the crossbar, and a hybrid form are compared.