Invited talk: Nanophotonic interconnection networks for performance-energy optimized computing

As the computational performance of microprocessors continues to grow, through the integration of an increasing number of processing cores, the interconnection network has become the central subsystem for providing the communications infrastructure among the on-chip cores, as well as to off-chip memory. This accelerated growth of multicore computational power is straining the capabilities of the interconnection network to deliver sufficient bandwidth to appropriately feed the processors, while severely widening the gap of the available off-chip memory access bandwidth. For many high-performance computing applications, the bandwidth available for both on- and off-chip communications can play a vital role in efficient execution, due to the use of data-parallel or data-centric algorithms. Electronic interconnected systems are increasingly bound by their communications infrastructure and the associated power dissipation of high-bandwidth data movement. Recent advances in chip-scale silicon photonic technologies have created the potential for developing optical interconnection networks that can offer highly energy efficient communications and significantly improve computing performance-per-Watt. This talk will examine the design and performance of photonic networks-on-chip architectures that support both on-chip communication and off-chip memory access in an energy efficient manner. Current challenges of inserting nanophotonic interconnect technologies into future computing systems will be discussed.