Title :
Ziggurat-based hardware Gaussian random number generator
Author :
Zhang, Guanglie ; Leong, Philip H W ; Lee, Dong U. ; Villasenor, John D. ; Cheung, Ray C C ; Luk, Wayne
Author_Institution :
Dept. of Comput. Sci. & Eng., Hong Kong Chinese Univ., Shatin, China
Abstract :
An architecture and implementation of a high performance Gaussian random number generator (GRNG) is described. The GRNG uses the Ziggurat algorithm which divides the area under the probability density function into three regions (rectangular, wedge and tail). The rejection method is then used and this amounts to determining whether a random point falls into one of the three regions. The vast majority of points lie in the rectangular region and are accepted to directly produce a random variate. For the nonrectangular regions, which occur 1.5% of the time, the exponential or logarithm functions must be computed and an iterative fixed point operation unit is used. Computation of the rectangular region is heavily pipelined and a buffering scheme is used to allow the processing of rectangular regions to continue to operate in parallel with evaluation of the wedge and tail computation. The resulting system can generate 169 million normally distributed random numbers per second on a Xilinx XC2VP3O-6 device.
Keywords :
Gaussian distribution; iterative methods; parallel architectures; pipeline processing; random number generation; sequential circuits; Ziggurat algorithm; buffering scheme; hardware Gaussian random number generator; iterative fixed point operation unit; parallel operation; pipeline computation; probability density function; wedge and tail computation; Circuit testing; Computational modeling; Computer architecture; Concurrent computing; Educational institutions; Hardware; High performance computing; Polynomials; Random number generation; Tail;
Conference_Titel :
Field Programmable Logic and Applications, 2005. International Conference on
Print_ISBN :
0-7803-9362-7
DOI :
10.1109/FPL.2005.1515734