Effect of pad stacks on dielectric layer failure during wire bonding

Mechanical failure of the dielectric layer induced by the stresses during wire bonding processes is of concern for design requirements placing active circuitry directly underneath the bond pad. An effective way to avoid dielectric layer cracking is to optimize the multi-layered pad stack structures. In this paper, the effect of pad stack structures on dielectric layer cracks is studied using experimental characterization and FEM analysis. A 3-D FEM model is proposed based on a qualitative analysis of the wire bonding process and typical dielectric layer cracks observed from experiments. In the FEM model, the boundary conditions, loading, mesh and failure criterion are carefully determined so to be most computationally-efficient. The maximum in-plane normal stress range, Deltasigma₁, is proposed here due to the brittleness of the thin dielectric layers and cyclic loading during the wire bonding process. The FEM model is validated by good correlations with real test data