A Low Spurious Direct Digital Synthesiser

A low spurious fine frequency step direct digital synthesiser (DDS) has been developed which utilises a patented spurious reduction technique that reduces spurious signals to below ¿80dB referenced to the output signal. The DDS is produced on a GaAs ASIC (Application Specific Integrated Circuit) and clocked at 300 MHz together with two high speed digital to analogue converters (DACs) and produces a usable output from DC to the Nyquist frequency of 150 MHz. The phase noise performance is <¿100dBc/Hz at 100 Hz from the carrier with the spurious reduction enabled. Frequency step size is less than 0.2 Hz and switching speed is of the order of 35ns due mainly to the intensive pipelining required inside the ASIC at these frequencies.