DocumentCode
2139574
Title
Yield modelling and yield enhancement for FPGAs using fault tolerance schemes
Author
Campregher, Nicola ; Cheung, Peter Y K ; Constantinides, George A. ; Vasilko, Milan
Author_Institution
Dept. of EEE, Imperial Coll. London, UK
fYear
2005
fDate
24-26 Aug. 2005
Firstpage
409
Lastpage
414
Abstract
This paper presents a revised model for the yield analysis of FPGA interconnect layers. Based on proven yield models, this work improves the predictions and assumptions of previously reported analysis. The model is then applied to three well known yield improvement schemes to quantify the enhancement offered by these schemes.
Keywords
fault tolerance; field programmable gate arrays; integrated circuit interconnections; integrated circuit yield; FPGA interconnect layers; fault tolerance; integrated circuit yield; yield enhancement; yield modelling; Design engineering; Educational institutions; Fault tolerance; Field programmable gate arrays; Inorganic materials; Kernel; Manufacturing; Metallization; Predictive models; Reflection;
fLanguage
English
Publisher
ieee
Conference_Titel
Field Programmable Logic and Applications, 2005. International Conference on
Print_ISBN
0-7803-9362-7
Type
conf
DOI
10.1109/FPL.2005.1515756
Filename
1515756
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