Fast FPGA placement using space-filling curve

Author

Banerjee, Pritha ; Bhattacharjee, Subhasis ; Sur-Kolay, Susmita ; Das, Sandip ; Nandy, Subhas C.

Author_Institution

Adv. Comput. & Microelectron. Unit, Indian Stat. Inst., Kolkata, India

fYear

2005

fDate

24-26 Aug. 2005

Firstpage

415

Lastpage

420

Abstract

In this paper, we propose a placement method for island-style FPGAs, based on recursive bi-partitioning followed by application of space-filling curves. Experimental results of our method show 55% improvement in cost, when compared to random initial placement of the popular tool VPR. The solutions thus obtained require 44.5% fewer moves during final iterative refinement by ultra-low temperature simulated annealing, whereas the quality of solution is on the average 0.1% better. This establishes the utility of the method for fast reconfiguration of FPGA based co-processors.

Keywords

coprocessors; field programmable gate arrays; integrated circuit layout; simulated annealing; FPGA based co-processor; FPGA placement; VPR; field programmable gate arrays; island-style FPGA; partitioning; recursive bi-partitioning; space filling curve; ultra-low temperature simulated annealing; Circuits; Field programmable gate arrays; Filling; Phased arrays; Programmable logic arrays; Reconfigurable logic; Routing; Simulated annealing; Switches; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications, 2005. International Conference on

Print_ISBN

0-7803-9362-7

Type

conf

DOI

10.1109/FPL.2005.1515757

Filename

1515757