Efficient FPGA implementation of Cordic algorithm for circular and linear coordinates

This paper proposes an efficient FPGA implementation of a common CORDIC architecture for circular and linear coordinates. The proposed circuit is derived from the single coordinate CORDIC architectures and the mapping on the Xilinx slices is fully detailed. Relative placed macros in VHDL have been designed to show the goodness of the proposed architecture. All the circuits have been implemented in Virtex-E and Virtex-II devices and the results show that the area of the common architecture is hardly larger than the area of a single coordinate or single mode CORDIC architecture. It is also shown that if a common architecture is modeled with RTL style its implementation requires the double of area and the maximum throughput decreases more than a half.