DocumentCode :
2140239
Title :
Latch-up in a BiCMOS technology
Author :
Deferm, L. ; Decoutere, S. ; Claeys, C. ; Declerck, G.
Author_Institution :
IMEC, Leuven, Belgium
fYear :
1988
fDate :
11-14 Dec. 1988
Firstpage :
130
Lastpage :
133
Abstract :
The presence of active bipolar transistors in a BiCMOS technology increases the latchup susceptibility compared to pure CMOS processes, due to the injection of carriers in the substrate when the device is switched into saturation. The firing of the parasitic thyristor due to transient forward signals on a diode and the influence of the active bipolar transistors on this firing are examined. It is shown that the use of a buried layer in the well, which is also the highly doped part of the collector of the active transistor, results in a strong increase of the latchup hardness. both transient and DC latchup have been investigated, and a good agreement between measured and simulated values is obtained by the use of a lumped model.<>
Keywords :
BIMOS integrated circuits; integrated circuit technology; transients; BiCMOS technology; DC latchup; active bipolar transistors; buried layer; latchup hardness; latchup susceptibility; lumped model; parasitic thyristor firing; saturation; substrate carrier injection; transient forward signals; BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Diodes; Parasitic capacitance; Pulse measurements; Testing; Thyristors; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1988. IEDM '88. Technical Digest., International
Conference_Location :
San Francisco, CA, USA
ISSN :
0163-1918
Type :
conf
DOI :
10.1109/IEDM.1988.32770
Filename :
32770
Link To Document :
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